Because AMD and Intel are the current major players in the x86 world (Cyrix's presence is nearly non-existent right now, the same with Centaur, and another upstart company, RISE, never made it to the PC world), I will focus on them, and their current mass-produced flagship chips.

When the Athlon was first introduced, it smashed its rival, the P3, in most everything. Aside from the Athlon's ability to execute far more instructions per clock cycle than the P3, the Athlon was also better fed. The Athlon's L1 cache was 4 times the size of the P3's, and thus the more numerous execution units on the Athlon could be better fed. Let's take a closer look:

Similarities:

• 3-cycle latency
• Harvard Architecture
• LRU for data
• Dual ported (meaning, it can do a read and a write to the cache at the same time)

Differences (Athlon vs. P3):

• 128kb Harvard Architecture (even split) vs. 32kb Harvard Architecture (even split)
• 2-way associative v. 4-way associative
• 64byte lines v. 32byte lines
• 3 Pre-decode-bits v. No pre-decode bits (saves time in decoding x86 code into the RISC-ish ops that current MPU's use - for the Athlon this adds 24kb of cache [to make up for the 3 bits used in each byte])

Now, moving to the L2 cache, at first glance, the L2 cache of the Athlon appears the same as that of the P3's, as both L2's:

• 512k of L2 cache (unified)
• Non-blocking
• Ran at ½ clock (Later Athlons used 2/5 and 1/3)
• Inclusive
• On cartridge
• 64 bit bus

However, the similarities end there. The differences in the L2 cache are as follows (Athlon first, P3 second - latencies taken from Aceshardware at [http://www.aceshardware.com/Spades/read.php?article_id=86 ]):

• 24-cycle L2 latency v. 27
• 2-way associative v. 4-way
• 64byte lines vs. 32byte lines

Now let us move to the cache styles of the P3 Coppermine and the Thunderbird Athlon. The L1 caches remain the same, however, the L2 architecture on both has changed.

Similarities:

• On-die
• 256kb

Differences (Athlon vs. P3):

• Exclusive v. Inclusive
• 16-way associative v. 8-way associative
• 8-entry 64-byte-line "victim cache" v. None - not an exclusive design
• 11-cycle latency (though, as high as 20 in worst case situations) v. 7 cycles
• 64-bit bus v. 256-bit bus
• Data sent every cycle v. every other cycle.