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  • IA-64 Explained
    September 13th, 2000
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    Introduction

    Lately, Intel has made a dizzying number of blunders in the x86 industry. The Coppermine Pentium III came out without a chipset that it was supposed to come with it (the i820), leaving the market only the venerable 440BX, which doesn't officially support a 133mhz bus, and the Apollo 133. When the i820 finally did come out, the chipset was riddled with problems such as the MTH issue. Intel has changed its stance on RAMBUS from it being the sole source of DRAM for the Pentium III and Pentium IV to being optional. To make matters worse for Intel, AMD has been sucking up all the voids left by these mistakes. What about outside the x86 market? How will Intel fare there?

    For about the last seven years, Intel has been working in conjunction with HP on a brand new ISA (Instruction Set Architecture) called IA-64 (Intel Architecture 64), which is an EPIC (Explicitly Parallel Instruction Computing) design (as opposed to a 'RISC' or 'CISC' design). The whole idea sprung from a project at HP about 11 years ago, when RISC was proliferating, and the thought of essentially doing out-of-order work being done by the compiler came out, so as to let the CPU use fewer transistors on out-of-order logic. Because of HP's influence in the IA-64 ISA, HP has incorporated a large number of instructions in IA-64 that are native PA-RISC instructions, and therefore, are machine-level compatible.

    I found this quote from arstechnica, which can be found here from: http://www.eet.com/story/OEG19981201S0003

    In his speech, Ditzel told some 300 conference attendees that RISC may be reaching the end of its "learning curve" after 20 years of use. He noted that RISC, which originally began as a rebellion against complexity, has itself become bogged down by massive instruction sets and large die sizes.

    "It was really fun in the early days; almost every computer company had a RISC chip," he said. "You did it because you could and you needed only a small design team."

    Nowadays, that's no longer the case, Ditzel argued. "Today [in RISC] we have large design teams and long design cycles," he said. "The performance story is also much less clear now. The die sizes are no longer small. It just don't seem to make as much sense."

    The result is the current crop of complex RISC chips. "Superscalar and out-of-order execution are the biggest problem areas that have impeded performance [leaps]," Ditzel said. "The MIPS R10,000 and HP PA-8000 seem much more complex to me than today's standard CISC architecture, which is the Pentium II. So where is the advantage of RISC, if the chips aren't as simple anymore?"

    So it seems that Intel agrees that too many resources are being used for OoO (out-of-order) processing, and that's why they have relegated that work to the compiler.

    Previously code-named 'Merced', the Itanium is Intel's initial venture into the 64-bit world of computing. Why venture from the x86 market which has served them so well? For one, because it's getting old, and while Intel will continue to support x86 for at least the next few years, the 32-bit extension of a 16-bit chip which was a hack of an 8 bit processor which was rooted in a 4 bit calculator chip... yeah, you get the idea. Intel thinks that x86 is getting a bit long-toothed (and maybe rightly so). When they started this, they had no idea that AMD would sneak up and begin to take leadership of the x86 world with their Athlon, nor did they know that AMD would create a 64-bit extension to the x86 ISA.

    Yet it seems that Intel wasn't quite ready to leave the x86 world altogether. They have included hardware support in the Itanium for the IA-32 (NOT for x86-64) architecture, as well as support for the PA-RISC architecture, which leaves the chip at well over 300 mm2 on a .18 micron process.

    Without further ado, let's get onto the processor specs:

    • 25.4 transistors (L3 cache non-inclusive)
    • 32K L1 cache
    • 92K L2 cache
    • 2-4mb L3 cache
    • Two Integer Units
    • Two Floating Point Units
    • Three Load/Store Units
    • 44 bit addressable bus space (16 Terabytes of addressable physical memory [460GX chipset is "limited" to 16 Gigabytes])
    • 128 (64-bit) General-Purpose Registers
    • 128 (64-bit) Floating-Point Registers
    • 64 (1-bit) Predication Registers
    • 10-stage pipeline

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    1. Introduction
    2. How It Works Part 1
    3. How It Works Part 2
    4. So How Will The Itanium Perform? Part 1
    5. So How Will The Itanium Perform? Part 2
    6. Bibliography
    Article Info
    Author: Paul Mazzucco
    Company: Intel
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