|
Bibliography
[1] Lo, Jack Lee-jay. "Exploiting Thread-Level Parallelism on Simultaneous Multithreaded Processors," PhD dissertation, University of Washington, 1998. http://www.cs.washington.edu/homes/jlo/papers/dissertation.ps
[2] DeMone, Paul. "Alpha EV8 (Part2): Simultaneous Multi-Threat. http://www.realworldtech.com/page.cfm?ArticleID=RWT122600000000. Dec 26, 2000.
[3] Diefendorff, Keith. "Power4 Focuses on Memory Bandwidth - IBM Confronts IA-64, Says ISA Not Important," Microprocessor Report, Oct. 6, 1999.
[4] Agarwal, Anat et al. "APRIL: A Processor Architecture for Multiprocessing"
[5] Mazzucco, Paul. "The Fundamentals of Cache." http://www.systemlogic.net/articles/00/10/cache Oct, 17, 2000. http://citeseer.nj.nec.com/rd/59311591%2C256536%2C1%2C0.25%2CDownload/http%253A%252F%252Fciteseer.nj.nec.com/cache/papers2/cs/10874/http%253AzSzzSzwww.cs.berkeley.eduzSz%257EkubitronzSzpaperszSzalewifezSzpdfzSzisca-april.pdf/agarwal90april.pdf
[6] "MAJC Architecture tutorial," Sun Microsystems, White Paper. http://www.sun.com/microelectronics/MAJC/documentation/docs/majctutorial.pdf
[7] Alverson, et al. "The Tera Computer System." Tera Computer Company. http://www.cag.lcs.mit.edu/6.893-f2000/readings.html
[8] Tullsen, Dean M. et al "Simultaneous Multithreading: Maximizing On-Chip Parallellism." Department of Computer Science and Engineering, University of Washington. http://www.cs.washington.edu/research/smt/papers/ISCA95.ps
[9] Jack L. Lo, et al "Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading" http://www.cs.washington.edu/research/smt/papers/tlp2ilp.final.pdf
[10] Lo, Jack L. et al. "Software-Directed Register Deallocation for Simultaneous Multithreaded Processors." Dept. of Computer Science and Engineering University of Washington. http://www.cs.washington.edu/research/smt/papers/regDealloc.ps
[11] Hily, Sebastian et al. "Contention on 2nd Level Cache May Limit the Effectiveness of Simultaneous Multithreading." Campus Universitaire De Beaulie. ftp://ftp.irisa.fr/techreports/1997/PI-1086.ps.gz
[12] Akkary, Haitham et al. "The Case for Speculative Multithreading on SMT Processors." Intel Microprocessor Research Labs. http://link.springer-ny.com/link/service/series/0558/papers/1940/19400059.pdf
[13] Mazzucco, Paul. "Why Intel is TwoFaced." http://www.systemlogic.net/articles/01/1/intel/page7.php January 9th, 2000.
[14] Akkary, Haitham et al. "A Dynamic Multithreading Processor." http://iacoma.cs.uiuc.edu/CS497/SP7.pdf
[15] Akkary, Haitham. "A Dynamic Multithreading Processor," Ph.D. Dissertation, Department of Electrical and Computer Engineering, Portland State University, Technical Report PSU-ECE-199811, June 1998. http://www.ee.pdx.edu/~driscoll/techreports/PSU-ECE-199811.pdf
[16] Purser, Zach et al. "A Study of Slipstream Processors." North Carolina State University. Department of Electrical and Computer Engineering. http://www.tinker.ncsu.edu/ericro/slipstream/papers/slipstream_micro33.final.pdf
More resources on SMT can be found at http://www.cs.washington.edu/research/smt.
>> Back Home
|
