07-28-01, 07:40 PM
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Registered User
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Join Date: Jun 2001
Location: California
Posts: 23
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Quote:
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Because the Athlon uses an exclusive design, SMP support requires the snooping of both the L1 and L2, so the requirements are more complex. I can't go much beyond that, because I haven't looked at it enough yet.
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The Athlon is an exclusive design, that is correct, does that mean that command snooping through caches is a necessary task... Nope, you can do a reference call on each, store it in chipset (as it does not require much memory) and access that from L1 bridge before making the call in the first place...
You seem to be a bit used to VIA's chipsets, have you been involved?
Patrick
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