Simplified for everyone who does not know (obviously does not include you):

You can access the caches via a high speed bus, called the chipset memory controller, if necessary you can store the processor cached references within that controller, making it easier to access, as the controller still has to respond to the CPU call, you can put a bit of extra memory into it that stores references to earlier calls...

This will mean that the CPU that has the cached info can either share it directly (if CPU-CPU calls are allowed by chipset) or you can send the data throughput directly to the latest cached...

VIA has some problems with this idea, PCRES does not, i thought you worked for VIA because your description of the Athlon cache subsystem sounds a lot like theirs... Meaning, i thought you were involved in VIA's chipset design...

Patrick

__________________
No question is to dumb if you are prepared for a technical answer...