We've been hearing a lot about SMT with the EV8 and P4 Xeon, so I thought I'd inagurate the first technical post about it....

I think Alpha said they can implement SMT on the EV8 with only a 10% overhead in die area...what changes need to be implemented in the datapath and control to enable SMT? I imagine you would need more PC registers and a larger register file, but what else? More execution units? A wider-issue decoder?

Also, would an SMT processor take advantage of the same multithreaded code designed for SMP machines?

Check out the front page friday

SMT doesn't require more functional units, what it does it to increase usage of the ones that are available. It allows more functional units to be added on without the same decreasing rate of returns on performance....that is, without SMT, adding more functional units tends to do little after about 3 or 4. This is a way of making it so that adding more functional units will show more performance when adding functional units than the alternative.

But just check back friday, there's a whole lot more in store....hehe.

Well, or you can check out the front page now:P

Thanks, it appears I have something to read while at work today.

I liked how you used Hennessey and Patterson's "Computer Architecture: a Quantitative Approach"...it was one of my textbooks for a computer architecture class I took last semester.