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      #1  
    Old 08-07-01, 05:17 PM
    pcres pcres is offline
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    What is the next step for AMD, i mean, what will the clawhammer bring, i have checked out some different descriptions for it... but all i can find is a longer pipeline and more execution units... And of course the addition of the X64 registers...

    What will this CPU bring to the 32 bit market and to the 64 bit market...

    Opinions please, facts if you have them...

    Thank you!

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      #2  
    Old 08-10-01, 10:31 AM
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    Quote:
    What is the next step for AMD, i mean, what will the clawhammer bring, i have checked out some different descriptions for it... but all i can find is a longer pipeline and more execution units... And of course the addition of the X64 registers...

    What will this CPU bring to the 32 bit market and to the 64 bit market...


    I never actually heard about "more execution units" per say, though that doesn't mean that it's not the case.

    From what little I konw of, it is (as I think you implied), the K8 (the first x86-64 core) is an Athlon derivative, which wasn't the case originally. I think that Dirk Meyer....well, I can't remember it was him or not, but one of the guys that was quite high-up in the Athlon design team, and was working on K8, jumped ship. So they had to scale back the ambitious plans....

    I'm kind of suprised that there are only 16 registers when in 64-bit mode. Surely there's a good reason for it, and that I simply don't understand/am not aware of it. However, all other high end 64-bit RISC chips have 32 registers, and the Alpha (RIP) has 32 registers dedicated for floating point itself.

    One thing many people were looking foward to was the Technical Floating Point unit that AMD has a patent for. From what I understand (which isn't necessarily all that much), it would basically allow a more RISC-like FPU, so when in x86-64 bit mode (not sure if that's long mode or not), that WOULD have allowed incredibly enhanced FPU performance of its IA-32 brethren. The downside is that, while AMD has a patent for it, they aren't using it in the Hammer series (well at least for clawhammer), and opted instead for SSE(2?) support.

    Between the lack of 64-bit registers (it's still regiser poor compared to risc chips), and the lack of Technical Floating Point, I'm led to believe that the Hammer series, at least at first, is geared much more towards the 32-bit side than the 64-bit side. I suspect that, at least for clawhammer, it will be very much like the antithesis of IA-64 (in terms of how it is used).

    The reason why I say this is that IA-64 boxes would be an incredible waste to be used as 32-bit machines, as the 32-bit performance is absolutely abysmal. I've heard that it is on the order of a 266mhz P2, even at 800mhz (Heh, I'd rather run FX32! on an Alpha than run in 32-bit mode on an Itanium, and the Alpha had no hardware dedicated to x86....*sigh*). So nobody will run it in 32-bit mode.

    Given that AMD has far less support (as in, they have very few applications ported to x86-64 compared to Intel with IA-64, which even still isn't that many), and the fact that there doesn't appear to be a huge incentive to move towards 64-bitness yet, I think the vast majority of the people will use Hammers in 32-bit mode. With SSE, they'll use applications that have been optimized for....you guessed it, IA-32. The advantage of the x86-64 was somewhat lost when AMD canned TPF.

    Another issue is that I believe that it is going to be in a .13 SOI processes. That's not exactly standard bulk CMOS, so they'll probably be quite a bit more expensive than regular athlons, simply from a production prspective, ignoring R&D....

    I think I now need to go back and find out what other rumours were flying around....
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      #3  
    Old 08-22-01, 09:57 AM
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    So nobody has any other thoughts? Dang....
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      #4  
    Old 08-22-01, 10:38 AM
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    euuhhh!!!

    I think you say everything paul , i cant be clearly
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