Could anyone provide information on how Coppermine-T is different from Coppermine?

I've not heard of it (but I've been busy anyway....). Any chance you could give me a link about where you heard of it?

Could you, perhaps, be mistaking it for Tualitin?

There is a Spanish site that refers to Coppermine-T

Here's the link if you can read spanish.

http://www.puissancepc.com/n/n1637.html

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Serious Soldier

Actually, that's french Checking it out now.

Well, AFAIK, Coppermine-T (or Tualitin) is a die-shrink of the Coppermine to .13 micron, which of course means a lower voltage (1.2v). It's supposed to have either timing's or signaling which is different from the regular Coppermine's (or something to that effect), and that the only "current" chipset which will support it is the venerable 440BX chipset.

There's going to be another revision of the i815 chipset, codenamed Almador with SDRAM support.

I know that the article linked showed the Tualitin and Coppermine-T as being different processors - I think that they are probably virtually the same.

The reasoning goes something like this:

The current Coppermine is somewhere around 90mm^2 (maybe even a tad bit smaller).

The die shrink should bring it to something along the lines of ~50mm^2 if left as is. That's getting really tiny for the number of pins that the P3 uses (I know it's socket 370, but I'm unsure if it uses all of them). What happens when processors get really small with high pin-counts is that it becomes difficult to find places to attatch the small wires that connect the core to the outside of the chip. This is known as being pad limited.

Intel has announced that the mobile version of a die-shrunken Coppermine will have 512Kb of L2 cache. This is useful for a number of reasons:

One, in that it means that it will be far less pad limited (it would increase the die size, maybe to something like 60 - 65mm^2).

The second issue is performance. The additional cache, of course, means a higher hit-rate, and therefore fewer accesses of main memory (always a good thing).

Third, this could actually reduce power consumption, as going off chip to the bus takes up substantial power, and by having a higher hit-rate, the power taken up by the cache my in-fact be low enough that it is more power-efficient (and performance efficient - a double bonus!) to have the additional cache so as not to go to main memory (and burn up power by doing so).

As far as the desktop, that is supposed to remain a 256Kb part. This also makes sense:

A 512Kb part, at a higher frequency (say, ~1.13ghz), would be a performance contender to the lower end P4's, which Intel does not want (but as they have no higher end mobile chip, that's ok). Worse yet, it would be cheaper due to lower construction costs, lower heat dissipation (won't need the ATX extensoin that the P4 requires for the heatsink), and will take cheaper SDRAM.

So it makes little sense to make a 512Kb die-shrunk P3, even if it were a slightly restricted platform (as discussed above). However, a 256Kb part might be slow enough in comparison to be useful as a lower end product, perhaps displacing the Celeron.

This would make sense, however the pad-limited issue as discussed before comes back into play. Here Intel can play a trick they've done before - simply use a laser to disable half the cache of a 512Kb version. If you want to read a bit more about that, read this page http://www.systemlogic.net/articles...ntel/page11.php of this article http://www.systemlogic.net/articles...intel/index.php.

Hymm....I think those are all my thoughts for now

French, Spanish, I don't know. Paul, I take it that you read
French. thanks for the update and your thoughts. I read that funny looking writing.....they call it Korean.

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Serious Soldier

One word: "Bablfish"

it here

http://www.tomshardware.com/cpu/01q2/010612/index.html

yeah, but that's peformance only, not actually telling us what's new in it

I remember reading about a week and a half ago (I think on Tom's Hardware Guide) that Intel *was* going to make 512KB-L2 cached Tualatins. There's also been some speculation that they might break it into a 256KB L2 cache and another 256KB L3 cache.

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"And knowing is half the battle!"

That doesn't make sense, as if you've seen the die photo (i'll link to it if you'd like) shows that it is exactly like that of the P3/celeron deal: half of it would simply be disabled.

The larger cached version would go either into mobile, or server market (maybe both), but a 512Kb version in the consumer market would seriously start to compete with the P4, even if the clock speed never went higher than 1.26Ghz. With the additional cache, it appears that the P3 is consistantly faster than a T-bird. I'm not sure if it's faster than a Palomino (256Kb L2), but we'll have to see

But, it looks like, so far, I was mostly right about it (I made that post before it was released).

What do you base this assumtion on?

I haven't seen anything that shows a PIII 1 Ghz being faster
than a AMD 1 Ghz. Quite the oppsite.

The AMD 1.3 will beat out the P4 1.7 in most all test. The PIII
is way behind.

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Serious Soldier

Doah, you caught my typo....I forgot to include the "Tualitin" part infront of it. I saw some benches a long while ago, not many, but they were indeed beating the T-bird.

Maybe you read that wrong?

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Serious Soldier